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Our Technology

Liquid Metal Ink – LMIx® – a unique atomic seed metallization chemistry suite enabling thin, conformal deposition of palladium, copper, gold and other PCB, semiconductor and bio-compatible metals by dipping, spraying, spinning or printing.

LMIx® | PVD-in-a-BottleTM

Enabling Multiple Critical Interconnect Platforms:

  • Ultra Fine-Line IC-Substrates
  • Glass Substrates and Through Glass Vias
  • Embedded Die
  • Flip Chip and Chiplet Interconnect
  • Fan-Out Wafer-Level Packaging
  • Through Silicon Via 2.5-3DIC
  • Ultra High-Density Interconnect PCBs
  •  

Nano-inks that enable the smallest 3D circuits on the widest range of substrates

Enabling the Highest Density Circuits on the Widest Range of Materials.

  • Ultra Thin: a few nanometers thick 
  • Ultra Dense: fully packed pinhole-free atomic film
  • Ultra Conformal: Complex surfaces at nanometer scale
  • Ultra Compatible: adheres to advanced substrates
  • Ultra Flexible: works with pure metals and alloys
LQDX_Density_3

Typical US Printed Circuit Boards
75/75 μm

LQDX_Density_2

Ultra High-Density Interconnect (UHDI) 25/25 μm

LQDX_Density_1

LQDX LMIx®
1/1 μm

Enabling Ultra-Dense Lines on the Most Advanced IC-Substrate Materials

10-20 nm seed Pd

1 μm line, 1 μm space

20 nm dense seed Pd

40 nm eless cu plate

Ultra-Thin Electroless Copper (40nm) + Ultra-Fine Lines with Preferred Grain Size and Structure

Ajinomoto Build-Up Film (ABF®) GL102

Facilitating Superior Adhesion On A Wide Range of Advanced Substrates

Enabling Superior Signal Integrity with Aluminum Clad Laminates (ACL™)

Adv-mSAP (LMI®)
10μm Width, 20μm Height

Traditional mSAP
25μm Width, 25μm Height

Extremely Thin Seed Layers =
Extremely Straight Side Walls

Extremely Low Aluminum Roughness =
Extremely Fine Lines with Strong Adhesion

Enabling Superior High Frequency Interconnect Performance

Extremely Thin Seed Layers =
Extremely Straight Side Walls

Extremely Fine Features

Facilitating 1μm Trace/Space with 5 μm Micro-Vias on ABF® and other Advanced Build-Up Films

Images Shown Include:

  • AT&S: Design
  • AJINIMOTO: ABF GL-102
  • LQDX: LMIx®
  • UYEMURA: E-less Copper
  • JSR: Liquid Photo Resist
  • SCREEN: Direct Imaging
  • OKUNO: ECD

5μm Micro-Vias on Advanced Ajinomoto Build-Up Film

5μm Diameter Micro-Via Seeding with LMIx®

5μm Diameter Plated Micro-Via

Ajimimoto ABF® GL-102

Enabling Silicon and Ceramic Substates with Through-Silicon Via and Fine Pitch Metallization

Silicon Substrates with 1μm Traces and 5μm Traces Through Silicon Vias

Enabling Glass Substrates & TGV with Low-Temperature (170C) Copper Metal

Schott Borofloat-33 Glass 650μm Thickness, 50μm Via,
13:1 AR TGV with LMIx® and Electroless Copper (Temp: 210C)

SEM Images

LQDX_Copper

Copper Layer

LQDX_Palladium

Palladium Layer

EDX Images

35nm Thick, Sa=50nm, Adhesion Class-5B, 100% Surface/Via Coverage

Facilitiating Direct Fan-Out Wafer-Level Patterning

Traces printed directly on mold compound and polyimide

Images Shown Include:

  • ALCONIX/LQDX: Design (7-20μm T/S)
  • SUMITOMO: EMC
  • LQDX: LMIx®
  • ATOTECH: E-less Cu
  • BREWER SCIENCE: Imaging
  • MARCH: Plasma
  • TOTECH: ECD

LQDX-Alconix-Brewer Science Design/Mask (7μm, 15μm, 20μm features). Max Temp 170C

Enabling Ultra High-Density Interconnect (UHDI) PCBs Using a 100% US Supply Chain

½ mil (12μm) patterns on 6-Layer UHDI RF circuit boards using 100% USA material set including LQDX ACLTM and LMI x® (Designed and built by USWC Crane)

Reliability Data - Thermal Stress, Convection Reflow Simulation

  • Test Method: IPC-TM-650 Method 2.6.27B, Table 5-2 (230℃)
  • Reflow Profile: 230℃
  • Quantity of Cycles: 6
  • Number of Nets per Coupon: 2
  • Failure Percentage (%): 5

Reliability Data - Thermal Shock

  • Test Method: IPC-TM-650 Method 2.6.7.2C, Continuity

  • Cycle Range: -55℃ – 170℃

  • Quantity of Cycles: 500

  • Number of Nets per Coupon: 2

  • Failure Percentage (%): 5

Reliability Data - Surface Insulation Resistance

  • Test Method: IPC-TM-650 Method 2.6.3.7

  • Test Conditions: 40℃ / 90%RH

  • Duration: 72 hours

  • Bias Voltage: 5 volts DC

  • Measurement Voltage : 5 volts DC

Requirement:

All SIR test patterns shall show a minimum resistance of 100 megohms (>108 ohms), beginning 24 hours after the chamber has stabilized at the elevated test condition.

Enabling the Next Node in

Semiconductor Interconnect

Our Technology Summarized  | Products and Licensing

LQDX Technology and Product Mix

LMIx® is sold as an ink, pre-coated on laminate or flex (CBF™,  ACL™), and/or as a per unit license fee for the process application (Adv-SAP™, EL-CAT™): whichever most closely fits the customer need.